The present invention relates to a PLL circuit utilizing a ΣΔ modulator.
In recent years, there has arisen a demand for PLL circuits employed in mobile communication equipment such as cellular phones to improve their channel switching speed and C/N characteristics to cope with the trends of increased integer ratio N and reduced power consumption in such equipment. In order to satisfy such demand, PLL circuits utilizing a ΣΔ modulator have been put in practical use. These PLL circuits utilizing a ΣΔ modulator are now required to improve their channel switching speed and C/N characteristics still further.
The channel switching time and C/N characteristics are important loop characteristics of a PLL circuit. Specifically, it is required to shorten the time required for switching from a certain lock-up frequency to another lock-up frequency and to reduce the phase noise contained in an output signal frequency.
In order to meet these requirements, fractional-N PLL frequency synthesizers (PLL circuits) using a fractional frequency division ratio of a comparison frequency divider configuring a PLL loop have recently been put in practical use. It is known that this type of fractional-N PLL circuits, which allows a reference signal frequency to be set high, is advantageous to improve the channel switching time and the C/N characteristics.
However, the fractional value of a fractional frequency division ratio is obtained equivalently and on an average by temporally varying the integer division value. Specifically, a fixed frequency division value N is periodically divided by N+1 to equivalently obtain a fractional frequency division ratio. For the case of 1/8 division, for example, eight dividing operations are implemented by repeating seven divisions by N and one division by N+1, while for the case of 3/8 division, eight dividing operations are implemented by repeating five divisions by N and three divisions by N+1.
However, when a comparison signal divided by such fractional-N operation is compared with a reference signal by means of a phase comparator, periodical phase errors occur due to periodical repetitions of N divisions and (N+1) divisions, which in turn causes spurious noise to occur in output signals of a voltage controlled oscillator.
Therefore, as one means for preventing occurrence of spurious noise associated with the fractional-N operation, a ΣΔ fractional-N PLL frequency synthesizer 100 having a multi-stage noise shaping (MASH) ΣΔ modulator as shown in FIG. 10 has been proposed. The ΣΔ modulator serves as means for preventing occurrence of spurious noise by randomly varying a frequency division value used for performing a fractional-N operation.
In FIG. 10, an oscillator 1 outputs to a reference frequency divider 2 a reference clock signal having a natural frequency based on oscillation of a crystal resonator. The reference frequency divider 2 is configured by a counter circuit, divides a reference clock signal based on a predetermined frequency division ratio and outputs a reference signal fr thus produced to a phase comparator 3.
The phase comparator 3 is provided with a comparison signal fp from a comparison frequency divider 4. The phase comparator 3 outputs a pulse signal according to a phase difference between the reference signal fr and the comparison signal fp to a charge pump 5.
The charge pump 5 outputs an output signal to a lowpass filter (LPF) 6 based on the pulse signal output from the phase comparator 3.
This output signal has a pulse component contained in its DC component, and the DC component varies in accordance with frequency variations of the pulse signal, while the pulse component varies based on the phase difference of the pulse signal.
The LPF 6 smooths the output signal of the charge pump 5 to remove any high frequency component therefrom and outputs an output signal thus obtained to a voltage controlled oscillator (VCO) 7 as a controlled voltage.
The VCO 7 outputs an output signal fvco with a frequency according to the controlled voltage to an external circuit as well as to the comparison frequency divider 4.
The frequency division ratio of the comparison frequency divider 4 is set to be varied arbitrarily by a ΣΔ modulator 8.
The ΣΔ modulator 8 is configured as a third-order modulator including n-bit integrators (Σ) 9a to 9c, differentiators (Δ) 10a to 10f configured by flip-flop circuits, and an adder 11. The integrators 9a to 9c and the differentiators 10a to 10f operate using the comparison signal fp from the comparison frequency divider 4 as a clock signal.
The integrator 9a is provided with a numerator value F for the ΣΔ modulator 8 from an external device (not shown). The integrator 9a accumulates the input value F based on the clock signal and outputs an overflow signal OF1 when the accumulated value becomes greater than a denominator value (modulo value) Q. After the overflow, the integrator 9a subtracts the denominator value Q from the accumulated value and continues to accumulate the input value F.
The denominator value (modulo value) Q is set to 2n, and the numerator value F is input as an (n−1)-bit digital signal when the power of the denominator value Q is n. The denominator values Q of the integrators 9a to 9c are an identical value, 1024 for example, and the numerator value F is 30.
The overflow signal OF1 from the integrator 9a is provided to the adder 11 via the differentiators 10a and 10b as an input signal a. The accumulated value X1 of the integrator 9a is provided to the integrator 9b. 
The integrator 9b performs an accumulating operation on an input signal of the accumulated value X1 and outputs an accumulated value X2 to the integrator 9c. An overflow signal OF2 output from the integrator 9b is provided to the adder 11 via the differentiator 10c as an input signal b, and also provided to the adder 11 via the differentiators 10c and 10d as an input signal c.
The integrator 9c performs an accumulating operation on an input signal of the accumulated value X2 and output an overflow signal OF3. The overflow signal OF3 is provided to the adder 11 as an input signal d, provided to the adder 11 via the differentiator 10e as an input signal 4, and also provided to the adder 11 via the differentiators 10e and 10f as an input signal f.
The differentiators 10a, 10b, and 10care inserted for correcting any deviation in timing of the input signals a to f caused by operation of the differentiators 10d, 10e, and 10f according to the clock signal.
The adder 11 implements the following computation:(+1)a+(+1)b+(−1)c+(+1)d+(−2)e+(+1)fbased on the input signals a to f. A coefficient to be multiplied by each of the input signals a to f is set based on a Pascal triangle.
FIG. 12 shows the computation results (excluding +N) of the computation operation of the adder 11 as described above. As shown in FIG. 12, the adder 11 produces random numbers which vary arbitrarily in the range from +4 to −3.
The adder 11 is provided with a fixed frequency division ratio N which has been preset. The adder 11 adds the above-mentioned computation result to the fixed frequency division ratio N and outputs the result to the comparison frequency divider 4.
Due to the operation of the adder 11 as described above, the frequency division ratio provided to the comparison frequency divider 4 varies randomly with respect to the fixed frequency division ratio N, for example as N, N+1, N, N−2, N+3, N−1, and N−1.
The comparison frequency divider 4 thus performs a fractional-N operation on an average based on the frequency division ratios received from the adder 11.
FIG. 11 shows a circuit equivalent to the ΣΔ fractional-N PLL frequency synthesizer shown in FIG. 10.
In this equivalent circuit, the configuration of a ΣΔ modulator 12 is slightly different from that of the ΣΔ modulator 8, while other configurations of the equivalent circuit are the same as in FIG. 10. In the ΣΔ modulator 12, integrators (Σ) 13a to 13c have similar configurations to the integrators 9a to 9c and perform a similar accumulating operation based on a numerator value F input thereto.
Differentiators 14a to 14e are each configured by a flip-flop circuit and operate using a comparison signal fp output from the comparison frequency divider 4 as a clock signal.
An overflow signal OF1 from the integrator 13a is provided to an adder 15a via differentiators 14a and 14b as an input signal a. An overflow signal OF2 from the integrator 13b is provided to an adder 15b via a differentiator 14c as an input signal d.
An overflow signal OF3 from the integrator 13c is provided to the adder 15b as an input signal e and also provided to the adder 15b via a differentiator 14d as an input signal f.
The adder 15b performs the computation b=d+e−f by adding the input signals e and d and subtracting the input signal f to obtain an output signal b and outputs the output signal b to the adder 15a. 
The output signal b of the adder 15b is also provided to the adder 15a via a differentiator 14e as an input signal c.
The adder 15a performs the computation a+b−c by adding the input signals a and b and then subtracting the input signal c and provides the result thus obtained to the adder 15c. 
The adder 15c adds the output signal from the adder 15a to the fixed frequency division ratio N provided by an external device and provides the resultant value to the comparison frequency divider 4.
Accordingly, the adders 15a and 15b of this ΣΔ modulator 12 perform the following computation operation:(+1)a+(+1)b+(−1)c+(+1)d+(−2)e+(+1)f.
As the result of such operation, random numbers varying arbitrarily in the range from +4 to −3 are output from the adder 15a. 
The adder 15c is provided with a fixed frequency division ratio N that has been preset. The adder 15c adds the aforementioned computation result to the fixed frequency division ratio N and outputs the result thus obtained to the comparison frequency divider 4.
As the result of such operation, the frequency division ratio input to the comparison frequency divider 4 varies with respect to the fixed frequency division ratio N randomly, for example as N, N+1, N, N−2, N+3, N−1, and N−1.
The comparison frequency divider 4 thus performs a fractional-N operation on an average based on the frequency division ratios output from the adder 15c. 
FIG. 12 shows an example of random numbers indicating the modulation width of modulated outputs from the third-order ΣΔ modulator 8 or the ΣΔ modulator 12 as shown in FIG. 10 and FIG. 11, respectively. FIG. 13 shows an example of random numbers produced by a fourth-order ΣΔ modulator. As seen from these two figures, as the order of ΣΔ modulators becomes greater, the width of variation of the output signals from the ΣΔ modulators becomes greater and the modulation width of the frequency division ratio at the comparison frequency divider 4 is increased.
FIGS. 14A to FIG. 14C show examples of random numbers produced by second-order to fourth-order ΣΔ modulators, respectively.
FIG. 15B shows a frequency spectrum of an output signal from a fractional-N PLL frequency synthesizer 100 employing a third-order ΣΔ modulator as described above, while FIG. 15A shows a frequency spectrum of an output signal from a fractional-N PLL frequency synthesizer employing a fourth-order ΣΔ modulator.
As seen from the comparison between FIGS. 15A and 15B, as the order of ΣΔ modulators becomes greater, the noise level that occurs when a PLL loop is locked is increased and a problem is posed that C/N characteristics are degraded.
In contrast, if the order decreases, the C/N characteristics are improved. However, ΣΔ modulation becomes instable, whereby the output signal is adversely affected.